10ECL77 VLSI LAB VTU Syllabus

VLSI LAB
Subject Code	: 10ECL77	IA Marks	: 25
No. of Practical Hrs/Week : 03		Exam Hours	: 03
Total no. of Practical Hrs.	: 42	Exam Marks	: 50

(Wherever necessary Cadence/Synopsis/Menta Graphics tools must beused)

PART - A

DIGITAL DESIGNASIC-DIGITAL DESIGN FLOW

1. Write Verilog Code for the following circuits and their Test Bench forverification, observe the waveform and synthesize the code with technological library with given Constraints*. Do the initial timing verification with gate level simulation.

1.An inverter

2.A Buffer

3.Transmission Gate

4.Basic/universal gates

5.Flip flop -RS, D, JK, MS, T

6.Serial & Parallel adder

7.4-bit counter [Synchronous and Asynchronous counter]

8.Successive approximation register [SAR]

*An appropriate constraint should be given

PART - B

ANALOG DESIGN

Analog Design Flow

1.Design an Inverter with given specifications*, completing the design flow mentioned below:

a.Draw the schematic and verify the following

i)DC Analysis

ii)Transient Analysis

b.Draw the Layout and verify the DRC, ERC

c.Check for LVS

d.Extract RC and back annotate the same and verify the Design

e.Verify & Optimize for Time, Power and Area to the given constraint***

2.Design the following circuits with given specifications*, completing the design flow mentioned below:

a.Draw the schematic and verify the following

i)DC Analysis

ii)AC Analysis

iii)Transient Analysis

b.Draw the Layout and verify the DRC, ERC

c.Check for LVS

d.Extract RC and back annotate the same and verify the Design.

i)A Single Stage differential amplifier

ii)Common source and Common Drain amplifier

3.Design an op-amp with given specification* using given differential amplifier Common source and Common Drain amplifier in library** and completing the design flow mentioned below:

a.Draw the schematic and verify the following

i)DC Analysis

ii). AC Analysis

iii)Transient Analysis

b.Draw the Layout and verify the DRC, ERC

c.Check for LVS

d.Extract RC and back annotate the same and verify the Design.

4.Design a 4 bit R-2R based DAC for the given specification and completing the design flow mentioned using given op-amp in the library**.

a.Draw the schematic and verify the following

i)DC Analysis

ii)AC Analysis

iii)Transient Analysis

b.Draw the Layout and verify the DRC, ERC

c.Check for LVS

d.Extract RC and back annotate the same and verify the Design.

5.For the SAR based ADC mentioned in the figure below draw the mixed signal schematic and verify the functionality by completing ASIC Design FLOW.

[Specifications to GDS-II]

*Appropriate specification should be given.

**Applicable Library should be added & information should be given to the Designer.

***An appropriate constraint should be given