10ES33 LD VTU Syllabus

LOGIC DESIGN
		(Common to EC/TC/EE/IT/BM/ML)
Sub Code	:	10ES33	IA Marks	:	25
Hrs/ Week	:	04	Exam Hours	:	03
Total Hrs.	:	52	Exam Marks	:	100

PART – A

UNIT 1:

Principles of combinational logic-1: Definition of combinational logic, Canonical forms, Generation of switching equations from truth tables,

Karnaugh maps-3, 4 and 5 variables, Incompletely specified functions (Don’t Care terms), Simplifying Max term equations. 6 Hours

UNIT 2:

Principles of combinational Logic-2: Quine-McCluskey minimization technique- Quine-McCluskey using don’t care terms, Reduced Prime Implicant Tables, Map entered variables. 7 Hours

UNIT 3:

Analysis and design of combinational logic - I: General approach,Decoders-BCD decoders, Encoders. 6 Hours

UNIT 4:

Analysis and design of combinational logic - II: Digital multiplexers- Using multiplexers as Boolean function generators. Adders and subtractors- Cascading full adders, Look ahead carry, Binary comparators. Design methods of building blocks of combinational logics.

7 Hours

PART – B

UNIT 5:

Sequential Circuits – 1: Basic Bistable Element, Latches, SR Latch,

Application of SR Latch, A Switch Debouncer, The S R Latch, The gated SR Latch, The gated D Latch, The Master-Slave Flip-Flops (Pulse-TriggeredFlip-Flops): The Master-Slave SR Flip-Flops, The Master-Slave JK Flip- Flop, Edge Triggered Flip-Flop: The Positive Edge-Triggered D Flip-Flop,Negative-Edge Triggered D Flip-Flop. 7 Hours

UNIT 6:

Sequential Circuits – 2: Characteristic Equations, Registers, Counters - Binary Ripple Counters, Synchronous Binary counters, Counters based on Shift Registers, Design of a Synchronous counters, Design of a SynchronousMod-6 Counter using clocked JK Flip-Flops Design of a Synchronous Mod-6Counter using clocked D, T, or SR Flip-Flops 7 Hours

UNIT 7:

Sequential Design - I: Introduction, Mealy and Moore Models, State Machine Notation, Synchronous Sequential Circuit Analysis and Design.

6 Hours

UNIT 8:

Sequential Design - II: Construction of state Diagrams, Counter Design.

6 Hours

TEXT BOOKS:

1.“Digital Logic Applications and Design” , John M Yarbrough, Thomson Learning, 2001.

2.“Digital Principles and Design “, Donald D Givone, Tata McGraw Hill Edition, 2002.

REFERENCE BOOKS:

1.“Fundamentals of logic design”, Charles H Roth, Jr; Thomson Learning, 2004.

2.“Logic and computer design Fundamentals”, Mono and Kim, Pearson, Second edition, 2001.

3.“Logic Design”, Sudhakar Samuel, Pearson/Saguine, 2007