LOGIC DESIGN LAB (Common to EC/TC/EE/IT/BM/ML)
Sub Code
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:
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10ESL38
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IA Marks
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:
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25
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Hrs/ Week
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:
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03
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Exam Hours
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:
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03
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Total Hrs.
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:
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42
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Exam Marks
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:
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50
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NOTE: Use discrete components to test and verify the logic gates. LabView can be used for designing the gates along with the above.
1.Simplification, realization of Boolean expressions using logic gates/Universal gates.
2.Realization of Half/Full adder and Half/Full Subtractors using logic gates.
3.(i) Realization of parallel adder/Subtractors using 7483 chip
(ii)BCD to Excess-3 code conversion and vice versa.
4.Realization of Binary to Gray code conversion and vice versa
5.MUX/DEMUX – use of 74153, 74139 for arithmetic circ uits and code converter.
6.Realization of One/Two bit comparator and study of 7485 magnitude comparator.
7.Use of a) Decoder chip to drive LED display and b) Priority encoder.
8.Truth table verification of Flip-Flops: (i) JK Master slave (ii) T type and
(iii)D type.
9.Realization of 3 bit counters as a sequential circuit and MOD – N counter design (7476, 7490, 74192, 74193).
10.Shift left; Shift right, SIPO, SISO, PISO, PIPO operations using 74S95.
11.Wiring and testing Ring counter/Johnson counter. 12. Wiring and testing of Sequence generator.
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