Lesson Plan IV SEM B-Section 10EC45 HDL Firdosh Parveen

         PROUDHADEVARAYA INSTITUTE OF TECHNOLOGY

T.B. Dam Hospet

                   ELECTRONICS AND COMMUNICATION ENGG DEPARTMENT.

SUB CODE:10EC45                               SUB:FANDAMENTAL OF HDL

STAFF NAME : Firdosh Parveen S           CLASS: IV SEM

Sl.No	Date	Topics to be covered
	01/2/12	UNIT1: Intruduction:Why HDl?,
	03/2/12	A Brief History of HDL
	03/2/12	structural of HDL Module
	04/2/12	Operators,data types
	06/2/12	Types of descriptions
	08/2/12	simulation and synthesis
	10/2/12	Brief comparison of VHDL and Verilog
	10/2/12	Unit2: Data-flow Description
	11/2/12,13/2/12	Highlights od Data flow descriptions
	15/2/12,17/2/12	structute of Data-Flow Description,
	17/2/12	Data Type-Vectors
	18/2/12,	UNIT 3 Behavioral Descrition
	22/2/12,24/2/12	highlights,structure of HDL behavioral description
	24/2/12,25/2/12	The VHDL variable-Asignment statement
	27/2/12	sequential statements.
	29/2/12	UNIT 4: Structural descriptions
	02/3/12	Highlights of structural desctription
	02/3/12	Organisation of the structural descriptions
	03/3/12	Binding
	05/3/12	state Machines
	07/3/12	Generate
	09/3/12	Generic
	09/3/12	Parameter statements
	10/3/12	UNIT5: Proceducers
	12/3/12	Tasks and Functions
	14/3/12	Highlights of Procedures
	19/3/12	tasks and Functions
	21/3/12	Procedures and Tasks,Functions
	24/3/12	Advanced HDL Descriptions:File
	26/3/12	Processing,Example of File Processing
	28/3/12	UNIT6: Mixed-Type Description :Why
	30/3/12	Mixed tupe decscription?
	30/3/12	VHDL user defined types
	31/3/12	VHDL packages,
	02/4/12,04/4/12	Miced-Type description examples
	06/04/12	UNIT 7: Mixed –Languuage descriptions
	06/4/12	Highlights of Mixed Language description
	07/4/12,09/4/12	How to invoke one language from the other,mixed language description
	11/4/12,13/4/12	examples,limitations of Mixed –Language description
	13/4/12	examples,limitations of Mixed –Language description
	14/4/12	UNIT8: synthesis Basis
	16/4/12	Highlights of synthesis
	18/4/12	sysnthesis information from entity and Module
	23/4/12	sysnthesis information from entity and Module
	25/4/12	Mapping process
	27/4/12	Mapping process
	27/4/12	Always in the Hardware Domain
	28/4/12	Always in the Hardware Domain
	30/4/12	PROGRAMES
	02/5/12	PROGRAMES
	04/5/12	PROGRAMES
	04/5/12	PROGRAMES