Monday, February 6, 2012

Lesson Plan IV SEM A-section 10EC45 HDL G. C. Manjunatha

         PROUDHADEVARAYA INSTITUTE OF TECHNOLOGY
T.B. Dam Hospet
                   ELECTRONICS AND COMMUNICATION ENGG DEPARTMENT.

SUB CODE:10EC45                               SUB:FANDAMENTAL OF HDL
STAFF NAME : G. C. Manjunatha           CLASS: IV SEM

Sl.No
Date
Topics to be covered
  1.  
02/2/12
UNIT1:

Intruduction:Why HDl?,
  1.  
02/2/12
A Brief History of HDL
  1.  
03/2/12
structural of HDL Module
  1.  
04/2/12
Operators,data types
  1.  
07/2/12
Types of descriptions
  1.  
09/2/12
simulation and synthesis
  1.  
09/2/12
Brief comparison of VHDL and Verilog
  1.  
10/2/12
Unit2:
Data-flow Description
  1.  
11/2/12,14/2/12
Highlights od Data flow descriptions
  1.  
15/2/12,16/2/12
structute of Data-Flow Description,
  1.  
16/2/12
Data Type-Vectors
  1.  
17/2/12,
UNIT 3
Behavioral Descrition
  1.  
18/2/12,21/2/12
highlights,structure of HDL behavioral description
  1.  
23/2/12,23/2/12
The VHDL variable-Asignment statement
  1.  
24/2/12
sequential statements.
  1.  
25/2/12
UNIT 4:
Structural descriptions
  1.  
28/2/12
Highlights of structural desctription
  1.  
01/3/12
Organisation of the structural descriptions
  1.  
01/3/12
Binding
  1.  
02/3/12
state Machines
  1.  
03/3/12
Generate
  1.  
06/3/12
Generic
  1.  
08/3/12
Parameter statements
  1.  
08/3/12
UNIT5: Proceducers
  1.  
09/3/12
Tasks and Functions
  1.  
10/3/12
Highlights of Procedures
  1.  
13/3/12
tasks and Functions
  1.  
15/3/12
Procedures and Tasks,Functions
  1.  
15/3/12
Advanced HDL Descriptions:File
  1.  
20/3/12
Processing,Example of File Processing
  1.  
22/3/12
UNIT6:
Mixed-Type Description :Why
  1.  
22/3/12
Mixed tupe decscription?
  1.  
243/12
VHDL user defined types
  1.  
27/3/12
VHDL packages,
  1.  
29/3/12,29/3/12
Miced-Type description examples
  1.  
30/3/12
UNIT 7:
Mixed –Languuage descriptions
  1.  
31/3/12
Highlights of Mixed Language description
  1.  
03/4/12,05/4/12
How to invoke one language from the other,mixed language description
  1.  
05/4/12,07/4/12
examples,limitations of Mixed –Language description
  1.  
10/4/12
examples,limitations of Mixed –Language description
  1.  
12/4/12
UNIT8:
synthesis Basis
  1.  
12/4/12
Highlights of synthesis
  1.  
13/4/12
sysnthesis information from entity and Module
  1.  
14/4/12
sysnthesis information from entity and Module
  1.  
17/4/12
Mapping process
  1.  
26/4/12
Mapping process
  1.  
26/4/12
Always in the Hardware Domain
  1.  
27/4/12
Always in the Hardware Domain
  1.  
28/4/12
PROGRAMES
  1.  
03/5/12
PROGRAMES
  1.  
05/5/12
PROGRAMES
  1.  
04/5/12
PROGRAMES


TEXT BOOKS:
1. HDL Programming (VHDL and Verilog)- Nazeih M.Botros- John
Weily India Pvt. Ltd. 2008.

REFERENCE BOOKS:
1. Fundamentals of  HDL – Cyril P.R. Pearson/Sanguin 2010. 
2. VHDL -Douglas perry-Tata McGraw-Hill
3. A Verilog HDL Primer- J.Bhaskar – BS Publications
4. Circuit Design with VHDL-Volnei A.Pedroni-PHI 




HOD                                                                                             STAFF INCHAGRE